Liao Cheng Chieh Resume Portfolio

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Biography

I have about 2 years of working experience as a Digital IC Design Engineer at AUO Corp., which benefits me with the knowledge of IC design from RTL logic design to synthesis and verification. In addition, I have experience in high-speed interfaces (SerDes) on FPGA, such as VX1 and LVDS.

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Projects
Completed

Years of
experience

Paper
Published

3.0+

GPA

My Skills

Verilog/SystemVerilog

90%

Cadance

70%

Modelsim/Verdi

75%

HSpice

70%

Python

70%

Solidworks

85%

My Timeline

2022 - present

M.S.E. in Computer Engineering - Arizona State University

Special in VLSI design.

2020 - 2022

Digital IC Design Engineer - AUO Corp.

Developing and Maintaining IP for Timing controller (TCON ASIC), including image processing and color gamut adjustment functions.

2018 - 2020

M.S. in Graduate institute of Biomedical Electronics and Bioinformatics - National Taiwan University

• Developed an automatic microwell microfluidic system that can improve the clinical applicability of SERS-based rapid antibiotics susceptibility test (AST).

Feb. 2020

Visiting Student - University of Tokyo

Assisted in bacteria incubation and SERS signal analysis to improve bio-sensing.

2014 - 2018

B.S. in Department of Bioindustrial Mechatronics Engineering - National Chung Hsing University

Created planar ITO electromagnetic coils on a glass slide, which has the potential to generate power for onchip microreactor.

Mar.-Aug. 2018

Exchange Student - Technische Universität Berlin

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My PortfolioMy Work

Here is some of my work that I've done in various programming languages.

Project Source